| CPC H04W 52/367 (2013.01) [H04W 52/42 (2013.01); H04W 72/0457 (2023.01)] | 9 Claims |

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1. An apparatus comprising:
at least one processor; and
at least one memory storing instructions that, when executed with the at least one processor, cause the apparatus to:
determine a channel bandwidth (CBW); and
based upon the determined CBW, determine a maximum power reduction (MPR) for the CBW in accordance with an allowed MPR as defined by an equation,
wherein the equation is:
![]() in an instance in which the determined CBW is in a group of less than 50 MHz CBWs;
wherein the equation is:
![]() in an instance in which the determined CBW is in a group of equal to or larger than 50 MHz CBWs; and
where CEIL(x,0.5 dB) means rounding x upwards to a closest multiple of 0.5 dB.
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