| CPC H04W 52/0203 (2013.01) | 20 Claims |

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1. An apparatus, comprising:
a first processor; and
a memory having instructions stored thereon that, when executed by the first processor, cause the apparatus to:
monitor a flow of data packets on a network plane;
calculate a packet rate of the flow of the data packets;
compare the packet rate with a first threshold value; and
in response to determining the packet rate is less than the first threshold value, modify a schedule of data packet flow to refrain from sending newly received packets to a worker thread executed by a second processor communicatively coupled with the apparatus and cause an operating state of the second processor to change from an active state to a sleep state in response to determining the worker thread processes all packets in a packet queue of the second processor until empty.
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