	US 12,464,267 B2
	Image sensor and camera module including the same
Daeyun Kim, Suwon-si (KR); and Hoyong Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 22, 2024, as Appl. No. 18/614,416.
Claims priority of application No. 10-2023-0039131 (KR), filed on Mar. 24, 2023; and application No. 10-2023-0049579 (KR), filed on Apr. 14, 2023.
Prior Publication US 2024/0323571 A1, Sep. 26, 2024
Int. Cl. H04N 25/76 (2023.01); G01S 7/481 (2006.01); G01S 17/894 (2020.01); H04N 13/289 (2018.01); H04N 25/53 (2023.01); H04N 25/705 (2023.01); H04N 25/77 (2023.01); H10F 39/00 (2025.01); H10F 39/18 (2025.01)

CPC H04N 25/7795 (2023.01) [G01S 7/4816 (2013.01); G01S 17/894 (2020.01); H04N 25/53 (2023.01); H04N 25/705 (2023.01); H04N 25/77 (2023.01); H10F 39/811 (2025.01); H04N 13/289 (2018.05); H10F 39/18 (2025.01)]

20 Claims

1. An image sensor comprising:

a demodulation clock generation circuit configured to generate M demodulation clock signals having N phases;

a buffer circuit comprising M signal lines configured to transfer each of the M demodulation clock signals; and

a pixel array comprising a plurality of pixels, wherein a pixel of the plurality of pixels has M taps and is configured to receive M demodulation signals passing through the M signal lines as inputs,

wherein each of the M demodulation signals is conducted by each of the M signal lines during an integration time of one frame of the pixel, and

wherein M and N are integers greater than or equal to 2.