US 12,464,054 B2
Microservice latency reduction
Dan Biederman, Saratoga, CA (US); Haichuan Tan, Santa Clara, CA (US); Pradeep Sakhamoori, Chandler, AZ (US); and Gabriel Arrobo Vidal, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2021, as Appl. No. 17/560,900.
Prior Publication US 2022/0116478 A1, Apr. 14, 2022
Int. Cl. H04L 67/61 (2022.01); G06F 11/34 (2006.01); H04L 41/5025 (2022.01); H04L 43/091 (2022.01); H04L 67/5682 (2022.01); H04L 67/51 (2022.01)
CPC H04L 67/61 (2022.05) [G06F 11/3466 (2013.01); H04L 41/5025 (2013.01); H04L 43/091 (2022.05); H04L 67/5682 (2022.05); H04L 67/51 (2022.05)] 25 Claims
OG exemplary drawing
 
1. A system for microservice latency reduction comprising:
at least one processor; and
memory including instructions that, when executed by the at least one processor, cause the at least one processor to perform operations to:
receive a request for execution of a microservice;
calculate an execution time for the microservice, wherein the execution time is an estimation of time to complete execution of the microservice;
identify a service level objective (SLO);
generate a latency hierarchy table including calculated latencies for processing units operating in a plurality of switching tiers of a network;
identify, by a network interface card, a processing unit of a computing node in a switching tier of the plurality of switching tiers for execution of the microservice based on the calculated execution time, the SLO, and the latency hierarchy table; and
transmit the request of execution of the microservice to the processing unit for instantiation.