US 12,463,794 B2
High-speed circuit combining AES and SM4 encryption and decryption
Pascal Van Leeuwen, Tilburg (NL)
Assigned to Rambus Inc., San Jose, CA (US)
Appl. No. 18/039,865
Filed by Rambus Inc., San Jose, CA (US)
PCT Filed Nov. 30, 2021, PCT No. PCT/US2021/061247
§ 371(c)(1), (2) Date Jun. 1, 2023,
PCT Pub. No. WO2022/125337, PCT Pub. Date Jun. 16, 2022.
Claims priority of provisional application 63/122,583, filed on Dec. 8, 2020.
Prior Publication US 2024/0097880 A1, Mar. 21, 2024
Int. Cl. H04L 9/00 (2022.01); H04L 9/06 (2006.01)
CPC H04L 9/0631 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method of performing cipher operations, comprising:
selecting, by a cipher accelerator circuit, whether to bypass a first affine transformation and a second affine transformation to process a first input data block according to an SM4 cipher and using an SM4 S-box table to produce a first partially SM4 ciphered data block and a first SM4 substituted data block that is supplied to an adjacent SM4 round processing circuit;
based on selecting to not bypass the first affine transformation, performing, by the cipher accelerator circuit, the first affine transformation applied to the first input data block to obtain a first transformed data block, wherein the first affine transformation includes multiplication of input data block by a first matrix and addition of a first translation vector;
based on selecting to not bypass the first affine transformation, performing, by the cipher accelerator circuit, a first byte substitution (S-box) operation according to the SM4 cipher and using the SM4 S-box table, the SM4 S-box operation being applied to the first transformed data block to obtain a substituted data block; and
based on selecting to not bypass the first affine transformation, performing, by the cipher accelerator circuit, the second affine transformation applied to the substituted data block to obtain a second transformed data block, wherein the second affine transformation includes multiplication of the substituted data block by a second matrix and addition of a second translation vector, and wherein the first and second matrices and the first and second translation vector are defined such that the second transformed data block is equal to the first input data block processed by a second S-box operation according to another symmetric cipher using S-box tables.