US 12,463,790 B2
System, method and apparatus for link training during a clock switch event
Ehud Shoor, Haifa (IL); Tsion Vidal, Bet Rimmon (IL); Uri Hermoni, Nordia (IL); Efraim Kugman, Givat Zeev (IL); Sarel Wechsler, Sapor (IL); Oren Salomon, Nahariya (IL); and Golan Cohen, Even-Yehuda (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 22, 2022, as Appl. No. 17/677,467.
Prior Publication US 2022/0182215 A1, Jun. 9, 2022
Int. Cl. H03D 3/24 (2006.01); H04L 7/00 (2006.01); H04L 7/027 (2006.01)
CPC H04L 7/027 (2013.01) [H04L 7/0004 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising: a receiver to receive training data from a transmitter;
a clock and data recovery (CDR) circuit coupled to the receiver, the CDR circuit to recover a recovered clock signal from the training data; and
a media access control (MAC) circuit coupled to the CDR circuit, wherein the MAC circuit is to send a clock switch indicator to the CDR circuit to cause the CDR circuit to halt tracking operation of the CDR circuit; wherein:
the apparatus comprises a re-timer;
the re-timer comprises:
a physical (PHY) circuit comprising the receiver and the CDR circuit; and
a link layer circuit coupled to the PHY circuit, the link layer circuit comprising the MAC circuit; and
the re-timer is to send a clock switch request to the transmitter when the MAC circuit detects the training data.