US 12,463,748 B2
Data receiving apparatus and method having blind deconvolution mechanism
Feng-Xiang Wang, Shanghai (CN); Ming-Yue You, Qinhuangdao (CN); Jyun-Wei Pu, Hsinchu County (TW); and Jia-Yi Zhuang, Shanghai (CN)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Jun. 16, 2023, as Appl. No. 18/210,838.
Claims priority of application No. 202211210938.7 (CN), filed on Sep. 30, 2022.
Prior Publication US 2024/0121028 A1, Apr. 11, 2024
Int. Cl. H04L 1/00 (2006.01); H04L 25/03 (2006.01)
CPC H04L 1/0059 (2013.01) [H04L 1/0038 (2013.01); H04L 1/0054 (2013.01); H04L 1/0071 (2013.01); H04L 25/03866 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A data receiving apparatus having blind deconvolution mechanism comprising:
a descrambling circuit configured to descramble received data received from an antenna according to an antenna assumption of the antenna and N data position assumptions within a transmission period to generate N groups of soft-bit data, wherein the received data is generated according to a convolution encoding process and comprises N data sub-blocks within the transmission period, the N data position assumptions in turn assume that a first data sub-block of the received data is a first original data sub-block of original data to that the first data sub-block is an N-th original data sub-block of the original data;
a storage circuit comprising N circular buffers each having a unit encoding length;
a soft-bit processing circuit configured to retrieve bit position information corresponding to the unit encoding length to determine a plurality of non-variable bit positions and a plurality of variable bit positions to perform a blind deconvolution process comprising:
storing and superimposing the N groups of soft-bit data corresponding to the N data position assumptions in a circular manner to generate N groups of superimposed results by the N circular buffers of the storage circuit; and
determining that a new assumed transmission period starts to keeping data corresponding to the non-variable bit positions in the N circular buffers and clearing data corresponding to the variable bit positions in the N circular buffers; and
a post-processing circuit configured to perform de-interleaving and decoding on the N groups of superimposed results of each of data sub-blocks to generate N groups of decoded results to perform redundancy check on the N groups of decoded results to generate N checked results;
wherein the soft-bit processing circuit determines that any one group of the N groups of decoded results passes the redundancy check according to the N checked results to outputs the group of decoded results that pass the redundancy check.