US 12,463,663 B2
Coding circuit, decoding circuit, coding method, decoding method and computer program
Takeshi Kakizaki, Musashino (JP); Masanori Nakamura, Musashino (JP); and Fukutaro Hamaoka, Musashino (JP)
Assigned to NTT, Inc., Tokyo (JP)
Appl. No. 18/271,134
Filed by NTT, Inc., Tokyo (JP)
PCT Filed Jan. 8, 2021, PCT No. PCT/JP2021/000470
§ 371(c)(1), (2) Date Jul. 6, 2023,
PCT Pub. No. WO2022/149259, PCT Pub. Date Jul. 14, 2022.
Prior Publication US 2024/0080045 A1, Mar. 7, 2024
Int. Cl. H03M 13/11 (2006.01); H03M 13/29 (2006.01)
CPC H03M 13/1125 (2013.01) [H03M 13/2978 (2013.01)] 3 Claims
OG exemplary drawing
 
1. An encoding circuit used for coherent digital signal processing, comprising:
a serial-parallel circuit configured to divide input data into a plurality of pieces of divided data by serial-parallel conversion;
a plurality of encoders configured to encode each of the pieces of divided data using codes with different decoding performance and coding rates; and
a bit conversion circuit configured to convert a bit sequence in order to make an amount of noise generated by a communication channel non-uniform among the plurality of pieces of divided data encoded by each of the plurality of encoders,
wherein the bit conversion circuit inputs the plurality of pieces of divided data encoded by each of the plurality of encoders via different lanes, and converts the bit sequence by calculating an exclusive OR of the input the plurality of pieces of divided data.