US 12,463,658 B2
On chip test architecture for continuous time delta sigma analog-to-digital converter
Ankur Bal, Greater Noida (IN); Abhishek Jain, Delhi (IN); and Sharad Gupta, New Delhi (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Dec. 26, 2023, as Appl. No. 18/396,542.
Application 18/396,542 is a continuation of application No. 17/723,225, filed on Apr. 18, 2022, granted, now 11,901,919.
Claims priority of provisional application 63/179,964, filed on Apr. 26, 2021.
Prior Publication US 2024/0235573 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 3/00 (2006.01)
CPC H03M 3/378 (2013.01) [H03M 3/46 (2013.01); H03M 3/496 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a test circuit configured to convert digital reference data representing an analog reference signal to digital reference data, to convert the digital reference data to a single-bit data stream, and to convert the single-bit data stream to an analog test signal; and
a continuous time delta sigma analog-to-digital converter coupled to the test circuit and including:
an input configured to receive the analog test signal from the test circuit;
conversion circuitry configured to convert the analog test signal to digital test data; and
an output configured to output the digital test data, wherein the test circuit is configured to receive the digital test data from the continuous time delta sigma analog-to-digital converter and to assess a performance of the continuous time delta sigma analog-to-digital converter based on the digital test data.