US 12,463,650 B2
Control of skew between multiple data lanes
Rupesh Singh, Ghaziabad (IN); and Ankur Bal, Greater Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Jul. 7, 2023, as Appl. No. 18/348,899.
Claims priority of provisional application 63/393,093, filed on Jul. 28, 2022.
Prior Publication US 2024/0039545 A1, Feb. 1, 2024
Int. Cl. H03L 7/195 (2006.01); H03K 3/356 (2006.01); H03L 7/199 (2006.01)
CPC H03L 7/195 (2013.01) [H03K 3/356026 (2013.01); H03L 7/199 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a first data lane control stage configured to:
control outputting first data over a first data lane based on a first data lane clock;
a second data lane control stage configured to:
control outputting second data over a second data lane based on a second data lane clock;
a first device associated with a system clock and configured to generate the first and second data for outputting over the first and second data lanes; and
a clock control stage including:
a first flip-flop configured to:
generate a first data lane clock reset signal; and
output the first data lane clock reset signal to the first data lane control stage, the first data lane clock reset signal being operative to set a timing of the first data lane clock of the first data lane control stage; and
a second flip-flop configured to:
generate a second data lane clock reset signal that is offset from the first data lane clock reset signal a fixed time duration that is an integer fraction of a cycle duration of the system clock; and
output the second data lane clock reset signal to the second data lane control stage, the second data lane clock reset signal being operative to set a timing of the second data lane clock of the second data lane control stage.