US 12,463,649 B2
Digital phase-locked loops (PLL) including closed-loop time-to-digital converter (TDC) gain calibration circuits and related methods
Ping Lu, Cary, NC (US); Minhan Chen, Cary, NC (US); and Shaishav A. Desai, San Diego, CA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Oct. 31, 2023, as Appl. No. 18/385,729.
Prior Publication US 2025/0141456 A1, May 1, 2025
Int. Cl. H03L 7/107 (2006.01); G04F 10/00 (2006.01); H03L 7/085 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/1075 (2013.01) [G04F 10/005 (2013.01); H03L 7/085 (2013.01); H03L 7/0991 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A calibrated digital phase-locked loop (DPLL), comprising:
a digitally controlled oscillator (DCO) circuit configured to generate a first output clock having a first frequency based on a control value; and
a feedback circuit configured to:
in a normal operating mode:
generate a first measurement of a first time interval corresponding to a phase difference between the first output clock and a reference clock; and
update the control value based on the first measurement; and
in a calibration operating mode:
keep the control value constant; and
adjust a first resolution of the first measurement to be closer to a nominal resolution.