US 12,463,647 B2
Level shifter and multi-voltage-domain circuits
Chandra Prakash Tiwari, Bangalore (IN); Tao Sun, Shanghai (CN); Hongyue Zhu, Shanghai (CN); Peiying Song, Shanghai (CN); and Yehao Shen, Shanghai (CN)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Nov. 21, 2023, as Appl. No. 18/515,621.
Claims priority of application No. 202221067743 (IN), filed on Nov. 24, 2022; and application No. 23175334 (EP), filed on May 25, 2023.
Prior Publication US 2024/0178840 A1, May 30, 2024
Int. Cl. H03K 19/0185 (2006.01); H03K 3/356 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 3/356113 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic circuit, configured to switchably generate an offset-bias output at a offset-bias voltage (VC) in response to at least an enable signal (EN) at a low voltage relative to the offset-bias voltage, and comprising:
a reference input terminal, configured to be connected to a reference voltage (GND);
a low-voltage-input terminal, configured to receive the enable signal at a first voltage;
a high-voltage-supply terminal, configured to receive power at a second voltage (VB);
an offset-bias output terminal, configured to output the offset-bias output, wherein the offset-bias voltage is less than the second voltage;
a voltage-offset circuit configured to generate the offset-bias voltage from the second voltage;
a bias circuit configured to switchably provide a bias current (Ib1) to the voltage-offset circuit; and
a high-voltage stand-off circuit, connected between the bias circuit and the voltage-offset circuit and configured to withstand a voltage difference between the second voltage (VB) and the reference voltage (GND);
wherein the voltage-offset circuit comprises:
a push-pull circuit;
a voltage-drop circuit comprising a series arrangement of a set of M−1 diode-connected p-FETs each having a gate-source voltage Vgs, connected between the high-voltage-supply terminal and a first node of the push-pull circuit to provide a voltage (M−1)·Vgs therebetween; and
a variable current source, connected between the high-voltage-supply terminal and the offset-bias output terminal and configured to provide a variable current at the offset-bias output terminal to stabilise the offset-bias voltage;
and wherein the push-pull circuit comprises a further p-FET having a gate-source voltage Vgs and at least one, N, n-FET connected between the high-voltage-supply terminal and the bias output terminal and having a threshold voltage Vt, and arranged to provide a voltage difference Vgs+N·(Vt) between the first node and the offset-bias output terminal;
wherein M is a natural number greater than 1 and N is a natural number greater than 0.