US 12,463,644 B2
Device, system and method to provide adaptive clock modulation with delay line circuits
Terry Remple, San Diego, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 7, 2022, as Appl. No. 17/834,669.
Prior Publication US 2023/0396249 A1, Dec. 7, 2023
Int. Cl. H03K 5/00 (2006.01); H03K 3/037 (2006.01); H03K 5/14 (2014.01); H03K 19/00 (2006.01); H03K 19/21 (2006.01)
CPC H03K 19/0016 (2013.01) [H03K 3/037 (2013.01); H03K 5/14 (2013.01); H03K 19/21 (2013.01); H03K 2005/00013 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a first delay line to receive a first signal, the first delay line comprising first segments each to provide a different respective one of first bits which are each based on the first signal;
sampler circuitry coupled to sample the first bits;
load circuitry coupled to receive the first bits from the sampler circuitry, the load circuitry to generate, based on the first bits, a thermometer code value comprising second bits and third bits;
a second delay line comprising second segments which are coupled each to receive a different respective bit of the second bits, wherein the second delay line is to output the second bits in a first sequence;
a third delay line comprising third segments which are coupled each to receive a different respective bit of the third bits, wherein the third delay line is to output the third bits in a second sequence; and
sequencer circuitry coupled to receive two bits each from a different respective one of the first sequence or the second sequence, wherein the sequencer circuitry is to generate a periodic signal based on each of the two bits.