US 12,463,641 B2
Synchronous triggering system, quantum control system and quantum computer
Weicheng Kong, Anhui (CN); Yongjie Zhao, Anhui (CN); Xuebai Li, Anhui (CN); and Liangchen Fan, Anhui (CN)
Assigned to Origin Quantum Computing Technology (Hefei) Co., Ltd., Hefei (CN)
Appl. No. 18/718,668
Filed by Origin Quantum Computing Technology (Hefei) Co., Ltd., Anhui (CN)
PCT Filed Oct. 27, 2022, PCT No. PCT/CN2022/127936
§ 371(c)(1), (2) Date Jun. 11, 2024,
PCT Pub. No. WO2023/116190, PCT Pub. Date Jun. 29, 2023.
Claims priority of application No. 202111587715.8 (CN), filed on Dec. 23, 2021; application No. 202111587945.4 (CN), filed on Dec. 23, 2021; and application No. 202111588000.4 (CN), filed on Dec. 23, 2021.
Prior Publication US 2025/0047281 A1, Feb. 6, 2025
Int. Cl. H03K 17/92 (2006.01); H03K 19/20 (2006.01)
CPC H03K 17/92 (2013.01) [H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A synchronous triggering system for a quantum control system, characterized by comprising:
a central control device;
a plurality of routing boards; and
a plurality of functional boards, wherein
the central control device is connected to the plurality of routing boards, configured for providing one or more sets of triggering signals to corresponding routing boards, and adjusting an initial time point for each set of triggering signals to output so that each of a plurality of chassis receives the triggering signals concurrently, and wherein each of the routing boards and the plurality of functional boards are provided inside one of the plurality of chassis;
each of the plurality of routing boards is connected to the plurality of functional boards, wherein communication lines from each routing board connected to the functional boards are of equal length, and the routing boards are configured for forwarding the triggering signals to the functional boards; and
each of the plurality of functional boards has an AND-gate chip and several data-processing devices, wherein the triggering signals arrive at the one or more data-processing devices simultaneously after being processed under an AND-operation of the AND-gate chip, so as to trigger the data-processing devices synchronously.