US 12,463,634 B2
Synchronizing turn-on/turn-off times of parallel power FETs
Edward Lee, Fullerton, CA (US); Ravi Ananth, Laguna Niguel, CA (US); Michael Chapman, Long Beach, CA (US); Marco Palma, Castagneto Po (IT); and Michael A. de Rooij, Playa Vista, CA (US)
Assigned to Efficient Power Conversion Corporation, El Segundo, CA (US)
Filed by Efficient Power Conversion Corporation, El Segundo, CA (US)
Filed on May 2, 2024, as Appl. No. 18/653,251.
Claims priority of provisional application 63/499,578, filed on May 2, 2023.
Prior Publication US 2024/0372545 A1, Nov. 7, 2024
Int. Cl. H03K 17/10 (2006.01); H03K 17/06 (2006.01); H03K 17/30 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 17/102 (2013.01) [H03K 17/063 (2013.01); H03K 17/302 (2013.01); H03K 19/01855 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A circuit for synchronizing the turn-on/turn-off times of parallel FETs, comprising:
a plurality of integrated circuits; and
a synchronizer;
wherein each integrated circuit comprises:
a power FET, wherein the power FET of the integrated circuit operates in parallel with the power FETs of other integrated circuits, and has a phase; and
a phase output signal representing the phase of the power FET; and
a phase detector, wherein the phase detector receives and compares the phase output signal of the integrated circuit and the phase output signal of another one of the integrated circuits, and provides at least one signal to the synchronizer regarding the relative turn-on times of the power FETs based upon the phase output signals;
wherein the synchronizer, in response to the at least one signal from each of the integrated circuits, reduces or increases the turn-on times of the power FETs such the turn-on times of the power FETs are synchronized.