US 12,463,631 B2
Charge pump gate driver circuit with an adjustable pump voltage for active DV/DT control
Hui Li, Tallahassee, FL (US); and Zhehui Guo, Tallahassee, FL (US)
Assigned to The Florida State University Research Foundation, Inc., Tallahassee, FL (US)
Filed by The Florida State University Research Foundation, Inc., Tallahassee, FL (US)
Filed on Sep. 27, 2023, as Appl. No. 18/373,744.
Claims priority of provisional application 63/416,208, filed on Oct. 14, 2022.
Prior Publication US 2024/0137014 A1, Apr. 25, 2024
Int. Cl. H03K 17/06 (2006.01); H03K 17/0412 (2006.01); H03K 17/687 (2006.01)
CPC H03K 17/063 (2013.01) [H03K 17/04123 (2013.01); H03K 17/6871 (2013.01); H03K 2217/0081 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A charge pump gate driver (CPGD) circuit with an adjustable pump voltage for active dv/dt control, comprising:
a first power supply that provides a positive voltage reference;
a second power supply that provides a negative voltage reference;
a first charge pump, wherein the first charge pump controls a turn-on switching speed of a power device, said first charge pump comprising two MOSFETSs, one diode (D1), and one flying capacitor (Cf1);
a second charge pump, wherein the second charge pump controls a turn-off switching speed of the power device, said second charge pump comprising two MOSFETS, one diode (D2), and one flying capacitor (Cf2); and
a totem-pole driver comprising two decoupling capacitors (Cd1 and Cd2) and split outputs to connect external ON and OFF gate resistors of the power device to the CPGD circuit,
wherein during a turn-on process a pulse width of a control signal (Sc1) of the first charge pump is adjusted so that the flying capacitor (Cf1) of the first charge pump is pre-charged to varying levels, allowing a voltage (vCf1) across the flying capacitor (Cf1) of the first charge pump to attain different magnitudes at a first time period (t1), then, a first one of the decoupling capacitors (Cd1) of the totem-pole driver is charged by discharging the flying capacitor (Cf1) of the first charge pump, which in turn pumps a voltage (vCd1) across the first one of the decoupling capacitors (Cd1) of the totem-pole driver to varying voltage levels during a second time subinterval [t1˜t2], wherein a different pump voltage of the voltage across the first one of the decoupling capacitors (Cd1) of the totem-pole driver at time period t2 leads to a varying gate current of the power device after the totem-pole driver is tied to a high output voltage at t2, providing different current rising rate and voltage falling rate of the power device, resulting in a faster switching speed, including an accelerated current rising rate, i.e., (t4-t3)<(t4x-t3), and an accelerated voltage falling rate, i.e., (t5-t4)<(t15x-t4x) of the power device,
wherein during a turn-off process a pulse width of a control signal (Sc2) is adjusted so that the flying capacitor (Cf2) of the second charge pump is pre-charged to varying levels, allowing a voltage (vCf2) across the flying capacitor (Cf2) of the second charge pump to attain different magnitudes at a first time period (t1), then a second one of the decoupling capacitors (Cd2) of the totem-pole driver is charged by discharging the flying capacitor (Cf2) of the second charge pump, which in turn pumps a voltage (vCd2) across the second one of the decoupling capacitors (Cd2) of the totem-pole driver to varying voltage levels during a second time subinterval [t1˜t2], wherein a different pump voltage of the voltage (vCd2) across the second one of the decoupling capacitors (Cd2) of the totem-pole driver at t2 leads to a varying gate current of the power device after the totem-pole driver is tied to a low output voltage at t2, providing different voltage rising rate and current falling rate of the power device, resulting in a faster switching speed, including an accelerated voltage rising rate, i.e., (t4-t3)<(T4X-t3), and an accelerated current falling rate, i.e., (t5-t4)<(t15x-t4x), and
wherein to prevent an overcharging issue, a value of Cf1 is selected to guarantee that a maximum pre-charged charge of Cf1 during a time subinterval [t0-t1] aligns with a total gate charge needed for the power device during the turn-on process, which is determined by:

OG Complex Work Unit Math
where Qgd is an equivalent gate-to-drain charge of SiC MOSFET at Vdc.