US 12,463,625 B2
Delay-adjusted digital-unit interface
Edward B. Stoneham, Las Vegas, NV (US)
Appl. No. 18/578,686
Filed by Edward B. Stoneham, Las Vegas, NV (US)
PCT Filed Jul. 12, 2022, PCT No. PCT/US2022/036761
§ 371(c)(1), (2) Date Jan. 11, 2024,
PCT Pub. No. WO2023/287744, PCT Pub. Date Jan. 19, 2023.
Claims priority of provisional application 63/221,012, filed on Jul. 13, 2021.
Prior Publication US 2025/0007503 A1, Jan. 2, 2025
Int. Cl. H03K 5/131 (2014.01); H03K 5/00 (2006.01)
CPC H03K 5/131 (2013.01) [H03K 2005/00058 (2013.01); H03K 2005/00163 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A delay-adjusted digital-unit interface comprising:
a first node configured to be connected to one end of a pull-up resistor, the pull-up resistor having another end connected to a first reference electrical potential, the first node being configured to be connected to a signal line of a transmission line connected to a first digital unit at a distal point on the transmission line, the first digital unit applying a high electrical potential alternating with a low electrical potential to the signal line of the transmission line during communication with a second digital unit;
a second node configured to be connected to a second reference electrical potential, to a signal-return line of the transmission line, and to a signal-return line of the second digital unit, the second reference electrical potential being less than the first reference electrical potential;
a third node configured to be connected to a signal line of the second digital unit, the second digital unit presenting between its signal line and its signal-return line a closed circuit alternating with an open circuit while the second digital unit is transmitting to the first digital unit and a continuous open circuit while the second digital unit is not transmitting to the first digital unit; and
an amplifier assembly configured to be connected between the first node and the third node, the amplifier assembly configured to transform between the high electrical potential on the first node and a medium electrical potential on the third node, the medium electrical potential being less than the high electrical potential and greater than the second reference electrical potential, the amplifier assembly including a switch, a sensing circuit, and a delay element, the sensing circuit including an amplifier, the sensing circuit being responsive to a change in the impedance between the signal line and the signal-return line of the second digital unit for operating the switch, the sensing circuit configured to close the switch at the end of a first delay period following presentation by the second digital unit of a closed circuit between its signal line and its signal-return line and to open the switch at the end of a second delay period following presentation by the second digital unit of an open circuit between its signal line and its signal-return line, the first delay period and the second delay period being governed by the delay element.