US 12,463,623 B2
Phase error compensation circuit and method for compensating phase error between reference clock and feedback clock
Wei-Hao Chiu, Hsinchu (TW); Song-Yu Yang, Hsinchu (TW); and Ang-Sheng Lin, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Aug. 15, 2023, as Appl. No. 18/234,346.
Claims priority of provisional application 63/426,318, filed on Nov. 17, 2022.
Prior Publication US 2024/0171162 A1, May 23, 2024
Int. Cl. H03K 5/01 (2006.01); H03L 7/08 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/01 (2013.01) [H03L 7/08 (2013.01); H03K 2005/00058 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A phase error compensation circuit for compensating a phase error between a reference clock and a feedback clock, comprising:
a first programmable delay circuit, configured to provide a first delay;
a second programmable delay circuit, configured to provide a second delay; and
at least one swapping circuit, coupled to the first programmable delay circuit and the second programmable delay circuit, configured to output a compensated reference clock and a compensated feedback clock according to the first delay, the second delay, the reference clock and the feedback clock;
wherein:
at a present cycle, the at least one swapping circuit is configured to apply the first delay to the feedback clock for generating the compensated feedback clock and apply the second delay to the reference clock for generating the compensated reference clock;
at a next cycle, the at least one swapping circuit is configured to apply the second delay to the feedback clock for generating the compensated feedback clock and apply the first delay to the reference clock for generating the compensated reference clock;
the first delay at the present cycle is substantially equal to the first delay at a last cycle, and the second delay at the present cycle is substantially equal to the second delay at the next cycle; and
the second delay at the present cycle is determined according to the phase error at the present cycle and the first delay at the present cycle, and the first delay at the next cycle is determined according to the phase error at the next cycle and the second delay at the next cycle.