US 12,463,609 B2
Dynamic amplifier with reduced sensitivity
Behnam Sedighi, La Jolla, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 19, 2022, as Appl. No. 17/821,115.
Prior Publication US 2024/0063765 A1, Feb. 22, 2024
Int. Cl. H03F 3/45 (2006.01); H03M 1/12 (2006.01)
CPC H03F 3/45183 (2013.01) [H03F 3/45475 (2013.01); H03M 1/122 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic amplifier comprising:
a pair of differential input nodes comprising a first input node and a second input node;
a pair of differential output nodes comprising a first output node and a second output node;
a first differential input transistor having a gate coupled to the first input node and having a drain coupled to a first intermediate node;
a second differential input transistor having a gate coupled to the second input node and having a drain coupled to a second intermediate node;
a first switch coupled between the first intermediate node and the first output node;
a second switch coupled between the second intermediate node and the second output node;
a third switch coupled between the first intermediate node and the second output node;
a fourth switch coupled between the second intermediate node and the first output node;
a fifth switch coupled between the first intermediate node and the second output node; and
a sixth switch coupled between the second intermediate node and the first output node, wherein:
for a first phase, the first switch, the second switch, the third switch, and the fourth switch are configured to be closed and the fifth switch and the sixth switch are configured to be open; and
for a second phase subsequent to the first phase, the first switch and the second switch are configured to be open and the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to be closed.