US 12,463,604 B2
Low noise amplifier incorporating Sutardja transformer
Sehat Sutardja, Las Vegas, NV (US)
Filed by Sehat Sutardja, Las Vegas, NV (US)
Filed on Apr. 1, 2022, as Appl. No. 17/711,935.
Claims priority of provisional application 63/170,375, filed on Apr. 2, 2021.
Prior Publication US 2022/0321067 A1, Oct. 6, 2022
Int. Cl. H03F 3/21 (2006.01); H01F 27/28 (2006.01); H03F 1/56 (2006.01)
CPC H03F 3/21 (2013.01) [H01F 27/28 (2013.01); H03F 1/565 (2013.01); H03F 2200/222 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01); H03F 2200/534 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A low noise amplifier comprising:
an input node configured to receive an input signal;
a first transistor and a second transistor each having a gate terminal, a source terminal and a drain terminal;
a transformer structure configured with:
a first winding pair, each winding of the first winding pair having a first end and a second end, the first ends of the first winding pair connected to the input node and one of the second ends connecting the first transistor source terminal and the other of the second ends connecting to the second transistor source terminal, wherein the windings that form the first winding pair are rotated, with respect to each other, by 180 degrees;
a second winding pair proximate the first winding pair, each winding of the second winding pair having a first end and a second end, the first ends of the second winding pair connected to a ground node and one of the second ends connecting the first transistor source terminal and the other of the second ends connecting to the second transistor source terminal, wherein the windings that form the second winding pair are rotated, with respect to each other, by 180 degrees;
a third winding pair proximate the first winding pair, each winding of the third winding pair having a first end and a second end, the first ends of the third winding pair connected to a bias signal source and one of the second ends connecting the first transistor gate terminal and the other of the second ends connecting to the second transistor gate terminal; and
an output node connected to the first transistor drain terminal and the second transistor drain terminal.