US 12,463,525 B2
High-side n-type power transistor gate driving techniques without a bootstrap capacitor
Taewoo Kwak, San Diego, CA (US); and Joseph Dale Rutkowski, Chandler, AZ (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 22, 2022, as Appl. No. 17/934,487.
Prior Publication US 2024/0106318 A1, Mar. 28, 2024
Int. Cl. H02M 1/08 (2006.01); H02M 3/158 (2006.01); H03K 17/687 (2006.01)
CPC H02M 1/08 (2013.01) [H02M 3/1582 (2013.01); H03K 17/6871 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A switched-mode power supply (SMPS) circuit comprising:
a buck converter including a high-side transistor having a drain coupled to an input voltage node;
a pulldown gate driver having an output coupled to a gate of the high-side transistor;
a pulse generator having an output coupled to an input of the pulldown gate driver; and
a first switch coupled between the gate and a source of the high-side transistor, wherein the pulse generator and the pulldown gate driver each have a first power supply input coupled to a reference potential node of the SMPS circuit;
a first level shifter having an output coupled to an input of the pulse and a first power supply input coupled to the reference potential node of the SMPS circuit; and
wherein the first level shifter, the pulse generator, and the pulldown gate driver each have a second power supply input coupled to the input voltage node.