US 12,463,427 B2
Method and circuit for an integrated DC converter in an AC battery
Sven Lill, Lauffen (DE); and Eduard Specht, Bruchsal (DE)
Assigned to DR. ING. H.C. F. PORSCHE AKTIENGESELLSCHAFT, Stuttgart (DE)
Filed by Dr. Ing. h.c. F. Porsche Aktiengesellschaft, Stuttgart (DE)
Filed on Aug. 1, 2023, as Appl. No. 18/362,979.
Claims priority of application No. 10 2022 120 021.3 (DE), filed on Aug. 9, 2022.
Prior Publication US 2024/0055858 A1, Feb. 15, 2024
Int. Cl. H02J 3/18 (2006.01); H02M 3/00 (2006.01)
CPC H02J 3/1857 (2013.01) [H02M 3/01 (2021.05)] 15 Claims
OG exemplary drawing
 
1. A method for ancillary supply in a modular multi-level converter, wherein the modular multi-level converter comprises a plurality of modules arranged in strands, wherein a respective module comprises at least two half bridges with semiconductor switches and at least one energy accumulator, which are interconnected in parallel, the method comprising:
forming, in the respective module, an at least single-core input terminal through respective center tapping in at least one half bridge on an input side, and forming an at least single-core output terminal through respective center tapping in at least one half bridge on an output side;
interconnecting the strands into at least one star point on the at least single-core input terminal of a first module in the respective strand;
forming, on the at least single-core output terminal of a last module in the respective strand, a respective phase of a supply voltage in a high-voltage system;
forming a respective ancillary terminal on a respective star point, wherein a common positive potential terminal having a respective positive potential of the first module is connected in the respective strand and a common negative potential terminal having a respective negative potential of the first module is connected in the respective strand; and
providing a first ancillary supply in the respective strand by connecting a selected converter to an associated selection from among the respective ancillary terminal, the common positive potential terminal, and the common negative potential terminal, and by associated control of the semiconductor switches of the at least one input-side half bridge of the first module.