US 12,463,180 B2
Monolithic chip stacking using a die with double-sided interconnect layers
Anup Pancholi, Hillsboro, OR (US); and Kimin Jun, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 29, 2023, as Appl. No. 18/374,972.
Application 18/374,972 is a continuation of application No. 18/239,549, filed on Aug. 29, 2023, granted, now 12,362,325.
Application 18/239,549 is a continuation of application No. 17/538,200, filed on Nov. 30, 2021, granted, now 11,784,165.
Application 17/538,200 is a continuation of application No. 16/633,543, granted, now 11,251,158, issued on Feb. 15, 2022, previously published as PCT/US2017/053291, filed on Sep. 25, 2017.
Prior Publication US 2024/0030188 A1, Jan. 25, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 25/50 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/92133 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06586 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first encapsulant having a top side above a bottom side, and a first sidewall and a second sidewall between the top side and the bottom side, the first encapsulant having a lateral width between the first sidewall and the second sidewall;
a first die having a top side and a bottom side, the bottom side facing toward the top side of the first encapsulant, the first die having a first interconnect layer on the bottom side, and a second interconnect layer on the top side;
a second encapsulant on the top side of the first encapsulant and laterally adjacent to the first die, the second encapsulant having the lateral width;
a redistribution layer coupled to the second interconnect layer of the first die, the redistribution layer in a third encapsulant, the third encapsulant on the second encapsulant and on the first die, and the third encapsulant having the lateral width;
a second die above the redistribution layer and the third encapsulant, the second die coupled to the redistribution layer by metal pillars;
a fourth encapsulant on the third encapsulant and laterally adjacent to the second die, the fourth encapsulant having the lateral width; and
interconnect structures beneath the bottom side of the first encapsulant.