US 12,463,170 B2
Semiconductor device and assortment of semiconductor devices with electrically conductive ribbon configurations
Mauro Mazzola, Calvenzano (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Aug. 5, 2022, as Appl. No. 17/881,921.
Claims priority of application No. 102021000021638 (IT), filed on Aug. 10, 2021.
Prior Publication US 2023/0049088 A1, Feb. 16, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/40 (2013.01) [H01L 23/49544 (2013.01); H01L 23/49558 (2013.01); H01L 23/49575 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/84 (2013.01); H01L 24/85 (2013.01); H01L 25/0655 (2013.01); H01L 2224/40247 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73221 (2013.01); H01L 2224/8412 (2013.01); H01L 2224/8512 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a mounting substrate comprising at least one die pad as well as a first electrically conductive pad and a second electrically conductive pad with a strip of insulating material between the first and second electrically conductive pads, wherein the strip of insulating material extends in a longitudinal direction with the first electrically conductive pad and the second electrically conductive pad lying on opposite sides of the strip of insulating material and being mutually electrically insulated by the strip of insulating material;
at least one further die pad in the mounting substrate, wherein the at least one die pad lies intermediate the at least one further die pad and the first and second electrically conductive pads;
a semiconductor die arranged on said at least one die pad in register with the strip of insulating material;
a further semiconductor die arranged on said at least one further die pad in register with the strip of insulating material;
a wire bonding pattern electrically coupling the further semiconductor die arranged on said at least one further die pad and the semiconductor die arranged on said at least one die pad, the wire bonding pattern in register with the strip of insulating material between the first electrically conductive pad and the second electrically conductive pad; and
a single electrically conductive ribbon electrically coupling the semiconductor die arranged on said at least one die pad with the first electrically conductive pad and the second electrically conductive pad, the single electrically conductive ribbon extending in said longitudinal direction in register with the strip of insulating material, wherein the single electrically conductive ribbon electrically contacts the first electrically conductive pad and the second electrically conductive pad that lie on opposite sides of the strip of insulating material and provides a current flow path from the semiconductor die arranged on said at least one die pad towards the first and second electrically conductive pads.