US 12,463,167 B2
Method of manufacturing semiconductor devices and corresponding semiconductor device
Antonio Bellizzi, Milan (IT); and Marco Rovitto, Milan (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jun. 6, 2022, as Appl. No. 17/833,233.
Claims priority of application No. 102021000014906 (IT), filed on Jun. 8, 2021.
Prior Publication US 2022/0392863 A1, Dec. 8, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01)
CPC H01L 24/19 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4871 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/367 (2013.01); H01L 23/5386 (2013.01); H01L 24/20 (2013.01); H01L 2224/214 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method, comprising steps performed in the following order:
providing a laminar substrate having an alternation of regions of electrically conductive material and laser direct structuring (LDS) material, respectively;
arranging a semiconductor chip on a region of LDS material in the laminar substrate, the semiconductor chip having a front active area facing towards the laminar substrate and a metallized back surface facing away from the laminar substrate;
forming an encapsulation of LDS material onto the laminar substrate to encapsulate the semiconductor chip, wherein the encapsulation of LDS material has an outer surface facing away from the laminar substrate, and wherein the metallized back surface of the semiconductor chip is exposed at said outer surface;
applying laser direct structuring processing to said region of LDS material in the laminar substrate to provide first electrically conductive lines towards the front active area of the semiconductor chip, said first electrically conductive lines comprising at least one first via extending through said region of LDS material in the laminar substrate to the front active area of the semiconductor chip; and
applying laser direct structuring processing to the encapsulation of LDS material to provide at least one second via extending through said encapsulation of LDS material to a region of electrically conductive material in said laminar substrate as well as a thermally conductive layer plated over the outer surface of the encapsulation of LDS material, wherein the thermally conductive layer extends in contact with the metallized back surface of the semiconductor chip exposed at said outer surface of the encapsulation of LDS material.
 
7. A method, comprising steps performed in the following order:
providing a laminar substrate having an alternation of regions of electrically conductive material and laser direct structuring (LDS) material, respectively;
arranging a plurality of semiconductor chips on a respective plurality of regions of LDS material in the laminar substrate, each semiconductor chip having a front active area towards the laminar substrate and a metallized back surface facing away from the laminar substrate;
forming an encapsulation of LDS material onto the laminar substrate to encapsulate the plurality of semiconductor chips, wherein the encapsulation of LDS material has an outer surface facing away from the laminar substrate, and wherein the metallized back surfaces of each of the plurality of semiconductor chips is exposed at said outer surface;
applying laser direct structuring processing to said regions of LDS material in the laminar substrate to provide first electrically conductive lines towards the front active area of each of the plurality of semiconductor chips, said first electrically conductive lines comprising a plurality of first vias extending through said regions of LDS material in the laminar substrate to the front active areas of the plurality of semiconductor chips;
applying laser direct structuring processing to the encapsulation of LDS material to provide a plurality of second vias extending through said encapsulation of LDS material to regions of electrically conductive material in said laminar substrate as well as a thermally conductive layer plated over the outer surface of the encapsulation of LDS material, wherein the thermally conductive layer extends in contact with the metallized back surfaces of the plurality of semiconductor chips exposed at said outer surface of the encapsulation of LDS material; and
cutting at said regions of electrically conductive material through the laminar substrate and said encapsulation of LDS material formed thereon, wherein said cutting removes said plurality of second vias extending through said encapsulation of LDS material and produces a plurality of singulated semiconductor devices that each comprise a respective portion of said thermally conductive layer.