US 12,463,154 B2
Semiconductor device
Yoshihiro Ohara, Tokyo (JP)
Assigned to Renesas Electronics Corporation, Tokyo (JP)
Filed by Renesas Electronics Corporation, Tokyo (JP)
Filed on Jun. 28, 2024, as Appl. No. 18/758,688.
Application 18/758,688 is a division of application No. 17/467,964, filed on Sep. 7, 2021, granted, now 12,062,627.
Claims priority of application No. 2020-152505 (JP), filed on Sep. 11, 2020.
Prior Publication US 2024/0363557 A1, Oct. 31, 2024
Int. Cl. H01L 23/60 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/60 (2013.01) [H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H01L 25/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06586 (2013.01)] 2 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor chip having a transistor region and a non-transistor region; and
a plurality of through vias formed in the non-transistor region,
wherein the plurality of through vias include:
an active via electrically connected to a circuit;
a floating via having a floating potential, the floating via being disposed between the active via and a boundary between the transistor region and the non-transistor region in a plan view, the floating via being configured to undergo dielectric breakdown during plasma charge-up to become electrically connected to a back surface wiring to which a ground potential is supplied, thereby protect the active via from plasma-induced damage; and
a damage via having a ground potential, the damage via being disposed between the active via and the boundary between the transistor region and the non-transistor region in a plan view, the damage via being formed by the floating via becoming electrically connected to the back surface wiring to which the ground potential is supplied due to the dielectric breakdown occurring in the floating via.