US 12,463,153 B2
Single die reinforced galvanic isolation device
Jeffrey Alan West, Dallas, TX (US); Thomas Dyer Bonifield, Dallas, TX (US); Toshiyuki Tamura, Ushiku (JP); and Yoshihiro Takei, Kashiwa (JP)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Sep. 30, 2022, as Appl. No. 17/958,040.
Prior Publication US 2024/0113042 A1, Apr. 4, 2024
Int. Cl. H01L 23/58 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/544 (2006.01)
CPC H01L 23/585 (2013.01) [H01L 21/762 (2013.01); H01L 23/53295 (2013.01); H01L 23/544 (2013.01); H01L 24/06 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/06102 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A microelectronic device, comprising:
a substrate;
an inorganic dielectric on the substrate;
an isolation device including:
a plateau on the inorganic dielectric, the plateau including:
a lower dielectric stack on the inorganic dielectric including at least one low stress silicon dioxide layer, and at least one high stress silicon dioxide layer;
a middle dielectric stack on the lower dielectric stack including a lower etch stop layer, and at least one layer of low stress silicon dioxide and at least one layer of high stress silicon dioxide over the lower etch stop layer;
an upper dielectric stack on the middle dielectric stack including at least one layer of low stress silicon dioxide, at least one layer of high stress silicon dioxide, at least one layer of silicon oxynitride, and at least one layer of silicon nitride; and
a lower isolation element in the lower dielectric stack;
an upper isolation element on the upper dielectric stack;
a dielectric protective overcoat on the upper isolation element;
an upper bond pad electrically connected to the upper isolation element; and
a lower bond pad electrically connected to the lower isolation element.