US 12,463,147 B2
Semiconductor device and method for manufacturing semiconductor device
Yoshihiro Tsukahara, Tokyo (JP); and Makoto Kimura, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Appl. No. 17/758,481
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
PCT Filed May 22, 2020, PCT No. PCT/JP2020/020392
§ 371(c)(1), (2) Date Jul. 7, 2022,
PCT Pub. No. WO2021/234969, PCT Pub. Date Nov. 25, 2021.
Prior Publication US 2023/0026891 A1, Jan. 26, 2023
Int. Cl. H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/552 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/552 (2013.01) [H01L 21/56 (2013.01); H01L 23/13 (2013.01); H01L 23/3121 (2013.01); H01L 23/5383 (2013.01); H01L 24/48 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/15162 (2013.01); H01L 2924/1517 (2013.01); H01L 2924/1815 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a multi-layer board which a wiring pattern and a grounding pattern are formed;
a plurality of semiconductor elements mounted on the multi-layer board;
an insulating sealing member provided on the multi-layer board and covering the plurality of semiconductor elements;
a metal film provided on the insulating sealing member;
in-groove metal provided in contact with a plurality of grooves extending from a side-surface upper end of the insulating sealing member to a side-surface lower end of the multi-layer board; and
in-hole metal provided in an inner wall of a hole penetrating through the insulating sealing member and extending to the multi-layer board, the in-hole metal contacting with the metal film and the grounding pattern.