US 12,463,142 B1
Integrating embedded memory with logic interconnects
Noriyuki Sato, Hillsboro, OR (US); Debraj Guhabiswas, Berkeley, CA (US); Tanay Gosavi, Portland, OR (US); Niloy Mukherjee, San Ramon, CA (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Oct. 1, 2021, as Appl. No. 17/449,797.
Application 17/449,797 is a continuation of application No. 17/449,750, filed on Oct. 1, 2021.
Int. Cl. H01L 23/538 (2006.01); G11C 11/22 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H10B 53/20 (2023.01)
CPC H01L 23/5389 (2013.01) [H01L 23/5384 (2013.01); H01L 24/82 (2013.01); H01L 25/0652 (2013.01); H10B 53/20 (2023.02); G11C 11/221 (2013.01); H01L 2225/06544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first region comprising:
a first conductive interconnect within a first level, the first conductive interconnect comprising a first lateral thickness; and
a second level above the first level, the second level comprising:
a memory device above the first conductive interconnect, the memory device comprising ferroelectric material or paraelectric material, wherein the memory device comprises a second lateral thickness and cylindrical shape;
an electrode structure coupled between the memory device and the first conductive interconnect, the electrode structure comprising a third lateral thickness, wherein the first lateral thickness and the third lateral thickness are respectively less than the second lateral thickness;
an etch stop layer comprising a dielectric material, the etch stop layer laterally surrounding the electrode structure;
a spacer on a sidewall of the memory device and on a portion of the electrode structure; and
a via electrode on the memory device; and
a second region adjacent to the first region, the second region comprising an interconnect structure, the interconnect structure comprising:
a second conductive interconnect within the first level;
a metal line within the second level; and
a via structure coupling the metal line with the second conductive interconnect, wherein at least a first portion of the via structure is adjacent to the etch stop layer, and wherein at least a second portion of the etch stop layer is on the second conductive interconnect, wherein the electrode structure has a first vertical thickness, the memory device has a second vertical thickness, the via electrode has a third vertical thickness, the via structure has a fourth vertical thickness, and the metal line has a fifth vertical thickness, wherein a sum of the first vertical thickness, the second vertical thickness and the third vertical thickness is substantially equal to a sum of the fourth vertical thickness and the fifth vertical thickness.