US 12,463,138 B2
Bit line and source line connections for a 3-dimensional array of memory circuits
Shohei Kamisaka, Kanagawa (JP); and Yosuke Nosho, Tokyo (JP)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Dec. 10, 2021, as Appl. No. 17/548,034.
Claims priority of provisional application 63/128,347, filed on Dec. 21, 2020.
Prior Publication US 2022/0199532 A1, Jun. 23, 2022
Int. Cl. H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/7684 (2013.01); H01L 21/76895 (2013.01); H01L 23/5283 (2013.01); H01L 23/53266 (2013.01); H01L 23/53271 (2013.01); H01L 23/5329 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A conductor-filled via formed between an interconnection conductor layer and two or more steps of a staircase structure in conjunction with a 3-dimensional array of memory cells formed above a planar surface of a semiconductor substrate, wherein (i) the staircase structure comprises a plurality of steps, (ii) each step comprises a plurality of layers, one on top of another, including, a source line layer at the top of each of the two or more steps of the staircase structure and an additional conductive layer; and (iii) the conductor-filled via is formed inside a spacer insulator that exposes the source line layers at the top of each of the two or more steps of the staircase structure and which insulates the conductor-filled via from the additional conductive layers in the two or more steps of the staircase structure.