US 12,463,136 B2
Integrated circuit devices including backside power rail and methods of forming the same
Myunghoon Jung, Clifton Park, NY (US); Wonhyuk Hong, Clifton Park, NY (US); Inchan Hwang, Schenectady, NY (US); Gunho Jo, Schenectady, NY (US); and Kang-Ill Seo, Albany, NY (US)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 28, 2022, as Appl. No. 17/936,106.
Claims priority of provisional application 63/336,335, filed on Apr. 29, 2022.
Prior Publication US 2023/0352408 A1, Nov. 2, 2023
Int. Cl. H01L 23/52 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H01L 23/5286 (2013.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit device, the method comprising:
providing a substrate that comprises a front surface and a back surface opposite the front surface, wherein first and second active regions, an isolation layer, and first and second sacrificial stack structures are provided on the front surface of the substrate, and wherein the isolation layer is between the first and second active regions, the first and second sacrificial stack structures respectively contact upper surfaces of the first and second active regions, and the first and second sacrificial stack structures each comprise a channel layer and a sacrificial layer;
forming an etch stop layer on an upper surface of the isolation layer;
replacing portions of the first and second sacrificial stack structures with first and second source/drain regions, respectively;
forming a front contact that contacts the first source/drain region, wherein the front contact comprises a front contact plug that is between the first and second source/drain regions;
forming a back-side insulator on a lower surface of the isolation layer; and
forming a back contact plug that is in the isolation layer and the back-side insulator and contacts a lower surface of the front contact plug,
wherein at least one of a portion of the front contact plug and a portion of the back contact plug is in the etch stop layer.