| CPC H01L 23/5226 (2013.01) [H01L 23/482 (2013.01); H01L 23/528 (2013.01); H01L 23/64 (2013.01)] | 8 Claims |
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1. An interconnect substrate, comprising:
a first interconnect layer;
a first insulating layer covering a side surface and a lower surface of the first interconnect layer;
a second insulating layer disposed on the first insulating layer and covering an upper surface of the first interconnect layer;
a second interconnect layer formed on a lower surface of the first insulating layer;
a third interconnect layer formed on an upper surface of the second insulating layer; and
a solder resist layer disposed on the second insulating layer and covering the third interconnect layer, an upper surface of the solder resist layer includes a chip mounting area where a semiconductor chip is to be mounted,
wherein the second interconnect layer includes a first ground plane, a first signal pad disposed in an opening provided in the first ground plane, and a first ground pad forming a portion of the first ground plane, and the first signal pad and the opening are each circular and concentric with each other,
wherein the third interconnect layer includes a second ground plane, a second signal pad disposed in an opening provided in the second ground plane, and a second ground pad forming a portion of the second ground plane, and the second signal pad and the opening provided in the second ground plane are each circular and concentric with each other,
wherein the first ground plane, the first insulating layer, an interconnect line of the first interconnect layer, the second insulating layer, and the second ground plane constitute a stripline, and a side surface of the interconnect line is covered with the first insulating layer,
wherein a side surface of the first ground plane is not covered with the first insulating layer, and a side surface of the second ground plane is not covered with the second insulating layer,
wherein the first interconnect layer includes:
interconnect lines;
a first pad electrically connected to the first signal pad through a first via interconnect extending through the first insulating layer;
a second pad electrically connected to the first ground pad through a second via interconnect extending through the first insulating layer;
a third pad electrically connected to the second signal pad through a third via interconnect extending through the second insulating layer; and
a fourth pad electrically connected to the second ground pad through a fourth via interconnect extending through the second insulating layer, a diameter of the first pad and a diameter of the second pad being smaller than a diameter of the first signal pad, a diameter of the third pad and a diameter of the fourth pad being smaller than a diameter of the second signal pad,
wherein the solder resist layer has a first opening exposing an upper surface of the second signal pad and a second opening exposing an upper surface of the second ground pad, the first opening and the second opening being located within the chip mounting area, and
wherein each of the first ground plane and the second ground plane is located under an entirety of the chip mounting area, except for openings provided therein, and the interconnect line that is part of the stripline is located under the chip mounting area, a terminal part of the interconnect line being the third pad electrically connected to the second signal pad.
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