| CPC H01L 23/49838 (2013.01) [H01G 4/228 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 23/5389 (2013.01); H01L 25/16 (2013.01); H01L 25/162 (2013.01); H01G 4/08 (2013.01); H01G 4/224 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19106 (2013.01)] | 20 Claims |
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1. A semiconductor package, comprising:
a substrate;
a dielectric layer on the substrate, the dielectric layer having an opening that exposes a portion of a top surface of the substrate;
a capacitor chip mounted on the substrate, the capacitor chip being within the opening of the dielectric layer in plan view;
connection terminals between the substrate and the capacitor chip, the connection terminals being on a bottom surface of the capacitor chip and connected to chip pads of the capacitor chip, the connection terminals connecting the substrate and the capacitor chip to each other;
dielectric patches on the substrate and in the opening of the dielectric layer; and
an under-fill filling a space between the substrate and the capacitor chip,
wherein the space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first region and the second region, the first and second regions being horizontally spaced apart from each other, a density of the connection terminals in the third regions is lower than a density of the connection terminals in each of the first region and the second region,
wherein the connection terminals are on the first region and the second region,
wherein the dielectric patches are on the third region and are completely and laterally surrounded by the under-fill, and
wherein a top surface of the dielectric layer is at a same level as top surfaces of the dielectric patches.
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