US 12,463,125 B2
Semiconductor package including post
Gongje Lee, Seoul (KR); and Sangkyu Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 30, 2022, as Appl. No. 18/060,226.
Claims priority of application No. 10-2022-0024071 (KR), filed on Feb. 24, 2022.
Prior Publication US 2023/0268265 A1, Aug. 24, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/105 (2013.01); H01L 23/49816 (2013.01); H01L 24/48 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1438 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first redistribution layer comprising a first via, a first redistribution pattern, and a first insulating layer;
a first semiconductor chip connected to the first redistribution layer via a chip connection terminal;
a lower post directly connected to the first redistribution layer;
an upper post connected to an upper surface of the lower post;
a first mold layer at least partially covering the first redistribution layer, the first semiconductor chip, the lower post, and the upper post; and
a second redistribution layer on the upper post and the first mold layer,
wherein the upper post has a width that gradually increases as the upper post extends from the lower post toward the second redistribution layer, and
wherein an upper surface of the upper post is coplanar with an upper surface of the first mold layer.