US 12,463,123 B2
Multi-chip system-in-package
Yusheng Lin, Phoenix, AZ (US); and Takashi Noma, Ota (JP)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US)
Filed on Apr. 29, 2022, as Appl. No. 17/661,420.
Claims priority of provisional application 63/184,386, filed on May 5, 2021.
Prior Publication US 2022/0359360 A1, Nov. 10, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/49827 (2013.01) [H01L 21/486 (2013.01); H01L 21/561 (2013.01); H01L 21/76898 (2013.01); H01L 23/3128 (2013.01); H01L 23/3157 (2013.01); H01L 23/481 (2013.01); H01L 24/02 (2013.01); H01L 24/06 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/16 (2013.01); H01L 25/18 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/06182 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a wafer-level interposer substrate having a first side and a second side opposite the first side, the wafer-level interposer substrate includes a support structure in an edge area on the first side;
forming a through-substrate via (TSV) extending between the first side and the second side of the wafer-level interposer substrate;
flip chip mounting at least two semiconductor die on the first side of the wafer-level interposer substrate;
encapsulating the at least two semiconductor die mounted on the first side of the wafer-level interposer substrate in a layer of molding material; and
singulating a wafer-level assembly of the wafer-level interposer substrate and the layer of molding material encapsulating the at least two semiconductor die mounted on the wafer-level interposer substrate to produce at least one individual system-in-package including the at least two semiconductor die.