US 12,463,122 B2
Semiconductor package
Pilsung Choi, Cheonan-si (KR); Donguk Kwon, Asan-si (KR); Sangsoo Kim, Cheonan-si (KR); Wooram Myung, Suwon-si (KR); Jiwon Shin, Daejeon (KR); and Sehun Ahn, Asan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 16, 2022, as Appl. No. 17/842,262.
Claims priority of application No. 10-2021-0139833 (KR), filed on Oct. 20, 2021.
Prior Publication US 2023/0119406 A1, Apr. 20, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/49811 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49833 (2013.01); H01L 24/29 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05599 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/2929 (2013.01); H01L 2224/29299 (2013.01); H01L 2224/81411 (2013.01); H01L 2224/81416 (2013.01); H01L 2224/81424 (2013.01); H01L 2224/81439 (2013.01); H01L 2224/81444 (2013.01); H01L 2224/81447 (2013.01); H01L 2224/81455 (2013.01); H01L 2224/81466 (2013.01); H01L 2224/83399 (2013.01); H01L 2924/014 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a lower substrate comprising a lower wiring layer;
a semiconductor chip disposed on the lower substrate, the semiconductor chip comprising:
a first surface facing the lower substrate,
connection pads electrically connected to the lower wiring layer, the lower wiring layer disposed on the first surface, and
a second surface opposite to the first surface;
an upper substrate disposed on the lower substrate and the semiconductor chip, the upper substrate comprising a lower surface on which support members protruding toward the second surface of the semiconductor chip are disposed, and the upper substrate further comprising an upper wiring layer;
a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer to the upper wiring layer;
an encapsulant filling a space between the lower substrate and the upper substrate and encapsulating at least a portion of each of the semiconductor chip and the connection structure;
adhesive members disposed on the second surface of the semiconductor chip such as to correspond to the support members, respectively, the adhesive members disposed in contact with each of the second surface and the support members; and
connection bumps disposed below the lower substrate and electrically connected to the lower wiring layer,
wherein each of the support members comprises an upper surface that faces towards the lower surface of the upper substrate,
wherein the upper surface of each of the support members is in contact with the lower surface of the upper substrate, and
wherein an uppermost portion of each of the adhesive members is lower than the upper surface of a corresponding support member from among the support members.