US 12,463,114 B2
Semiconductor chip including through electrode, and semiconductor package including the same
Ho Young Son, Icheon-si (KR); Sung Kyu Kim, Icheon-si (KR); and Mi Seon Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 25, 2024, as Appl. No. 18/615,528.
Application 18/615,528 is a continuation of application No. 18/489,557, filed on Oct. 18, 2023.
Application 18/489,557 is a continuation of application No. 18/103,346, filed on Jan. 30, 2023, granted, now 11,823,982, issued on Nov. 21, 2023.
Application 18/103,346 is a continuation of application No. 17/191,287, filed on Mar. 3, 2021, granted, now 11,594,471, issued on Feb. 28, 2023.
Claims priority of application No. 10-2020-0159887 (KR), filed on Nov. 25, 2020.
Prior Publication US 2024/0234255 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/481 (2013.01) [H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16146 (2013.01); H01L 2225/06513 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first semiconductor chip; and
a second semiconductor chip and a third semiconductor chip sequentially stacked over the first semiconductor chip,
wherein the first semiconductor chip comprises:
a first body with a first front surface;
a first signal through electrode in the first body;
a pair of first power through electrodes in the first body;
a first signal front connection electrode electrically connected with the first signal through electrode, wherein the first signal front connection electrode is disposed over the first front surface; and
a first power front connection electrode electrically connected with the pair of first power through electrodes, wherein the first power front connection electrode is disposed over the first front surface,
wherein the second semiconductor chip comprises:
a second body with a second front surface;
a second signal through electrode in the second body; and
a pair of second power through electrodes in the second body,
wherein the pair of first power through electrodes are electrically connected with the pair of second power through electrodes, and
wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip have a same size.