US 12,463,104 B2
Semiconductor package and method for manufacturing the same
Jun Woo Myung, Suwon-si (KR); and Gun Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 27, 2023, as Appl. No. 18/140,417.
Claims priority of application No. 10-2022-0112790 (KR), filed on Sep. 6, 2022.
Prior Publication US 2024/0079284 A1, Mar. 7, 2024
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01)
CPC H01L 23/3128 (2013.01) [H01L 21/565 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/1058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first redistribution structure including a first redistribution layer disposed therein;
a first semiconductor chip disposed on the first redistribution structure;
an insulating layer surrounding a sidewall of the first semiconductor chip on the first redistribution structure, the insulating layer is spaced apart from the first semiconductor chip in a horizontal direction;
a first connection structure extending through the insulating layer in a vertical direction perpendicular to the horizontal direction, the first connection structure is connected to the first redistribution structure, the first connection structure includes a first via disposed inside the insulating layer;
a second connection structure disposed between the first semiconductor chip and the first connection structure in the horizontal direction, the second connection structure extends through the insulating layer in the vertical direction, the second connection structure is connected to the first redistribution structure, the second connection structure includes a second via disposed inside the insulating layer; and
a molding layer covering the first semiconductor chip, a sidewall and an upper surface of the insulating layer on the first redistribution structure,
wherein at least a portion of the molding layer is disposed between the first via and the second via.