US 12,463,099 B2
Semiconductor package including test line structure
Tsung-Yang Hsieh, Taipei (TW); Chien-Chang Lee, Miaoli County (TW); Chia-Ping Lai, Hsinchu (TW); Wen-Chung Lu, Hsinchu (TW); Cheng-Kang Huang, Hsinchu (TW); Mei-Shih Kuo, Hsinchu (TW); and Alice Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/232,520.
Application 18/232,520 is a division of application No. 17/469,055, filed on Sep. 8, 2021.
Claims priority of provisional application 63/178,812, filed on Apr. 23, 2021.
Prior Publication US 2023/0386944 A1, Nov. 30, 2023
Int. Cl. H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01)
CPC H01L 22/32 (2013.01) [H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing an interposer comprising an interposer substrate, the interposer substrate having a plurality of conductive lines (RDLs) formed through at least a portion of the interposer substrate;
forming a first test line (TL) structure on the interposer, wherein forming the first TL structure comprises forming a first test line encapsulated in a TL dielectric layer, wherein forming the first TL structure results in an upper surface of the TL dielectric layer to extend towards an upper surface of the first test line and a lower surface of the TL dielectric layer to extend along a lower surface of the first test line, and wherein forming the TL structure comprises forming an opening in the first test line and forming the TL dielectric layer to extend through the opening;
disposing conductive bumps on portions of the first test line; and
coupling a device die of a die device structure to the conductive bumps, wherein a first portion of the first test line extends beyond a peripheral edge of the die device structure to provide an electrical interface with at least one of the device die and the interposer.