US 12,463,098 B2
Semiconductor device and production method for semiconductor device
Shingo Kabutoya, Tsukuba (JP)
Assigned to KYOCERA Corporation, Kyoto (JP)
Appl. No. 17/434,034
Filed by KYOCERA Corporation, Kyoto (JP)
PCT Filed Feb. 28, 2020, PCT No. PCT/JP2020/008452
§ 371(c)(1), (2) Date Aug. 26, 2021,
PCT Pub. No. WO2020/179702, PCT Pub. Date Sep. 10, 2020.
Claims priority of application No. 2019-037198 (JP), filed on Mar. 1, 2019.
Prior Publication US 2022/0139780 A1, May 5, 2022
Int. Cl. H01L 21/78 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/78 (2013.01) [H01L 23/564 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A production method for a semiconductor device, comprising:
forming a surface electrode metal joined to portions of a surface of a semiconductor layer on a wafer on which multiple semiconductor devices are attached;
forming an outermost trench of the semiconductor device by digging the semiconductor layer outside an outer edge of the surface electrode metal,
wherein the outer edge of the surface electrode metal is located at a position separated inward from the outermost trench, such that the outermost trench is not covered by the surface electrode metal;
forming a trench in a surface of the semiconductor layer under the surface electrode metal;
embedding a polysilicon in the trench,
wherein the surface electrode metal are directly connected to the polysilicon;
oxidizing the surface of the semiconductor layer on which the trench and outmost trench are formed to form an insulating film in the trench to cover an entire inner surface of the trench,
wherein the surface electrode metal covers an entire peripheral surface of each of the trench, the polysilicon, and the insulating film;
dicing of cutting out individual semiconductor devices from the wafer; and
checking a kerf by checking a distance between the outermost trench and a chip contour position of the semiconductor device after the dicing.