US 12,463,089 B2
Semiconductor devices and methods of manufacturing thereof
Te-Hsin Chiu, Miaoli County (TW); Shih-Wei Peng, Hsinchu (TW); Wei-An Lai, Taichung (TW); and Jiann-Tyng Tzeng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 29, 2023, as Appl. No. 18/344,565.
Application 18/344,565 is a division of application No. 17/533,000, filed on Nov. 22, 2021, granted, now 11,721,576.
Claims priority of provisional application 63/140,331, filed on Jan. 22, 2021.
Prior Publication US 2023/0352339 A1, Nov. 2, 2023
Int. Cl. H01L 21/762 (2006.01); H01L 21/3115 (2006.01); H01L 21/66 (2006.01); H01L 21/74 (2006.01)
CPC H01L 21/76243 (2013.01) [H01L 21/31155 (2013.01); H01L 21/743 (2013.01); H01L 22/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system for testing a semiconductor structure, comprising:
the semiconductor structure, including:
a semiconductor substrate including a first side and a second side opposite the first side;
a doped layer buried below the first side;
a plurality of gate-all-around (GAA) transistors disposed over the first side wherein each GAA transistor includes: a stack of channel layers extending vertically from the semiconductor substrate; a gate structure wrapping around the stack of channel layers; and source/drain structures on opposite sides of the gate structure; wherein each of the GAA transistors is coupled to the doped layer through a respective doped semiconductor contact structure extending vertically through the semiconductor substrate; and
a plurality of interconnect structures coupled to the source/drain transistors over the first side;
a tester disposed over the first side and configured to apply an electrical signal to the doped layer through the interconnect structures; and
a testing device disposed over the second side and configured to test electrical connections in the semiconductor structure in response to the applied electrical signal.