US 12,463,088 B2
Selective etches for reducing cone formation in shallow trench isolations
Karen Hildegard Ralston Kirmse, Richardson, TX (US); and Jonathan Philip Davis, Allen, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Dec. 6, 2023, as Appl. No. 18/530,423.
Application 17/478,306 is a division of application No. 16/567,661, filed on Sep. 11, 2019, granted, now 11,171,035, issued on Oct. 20, 2021.
Application 18/530,423 is a continuation of application No. 17/478,306, filed on Sep. 17, 2021, granted, now 11,908,729.
Application 16/567,661 is a continuation of application No. 15/852,171, filed on Dec. 22, 2017, granted, now 10,453,738.
Prior Publication US 2024/0105501 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/762 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H10D 62/10 (2025.01)
CPC H01L 21/76229 (2013.01) [H01L 21/3065 (2013.01); H01L 21/308 (2013.01); H01L 21/31116 (2013.01); H10D 62/115 (2025.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a semiconductor substrate having a surface;
a first isolation structure along the surface, the first isolation structure having a first feature dimension and a first sidewall slope;
a second isolation structure along the surface, the second isolation structure having a second feature dimension greater than the first feature dimension, the second isolation structure having a second sidewall slope within a 15 degrees of deviation from the first sidewall slope;
a transistor structure laterally isolated by the first isolation structure; and
a circuit component integrating the second isolation structure;
wherein the first feature dimension includes a first trench width; and the second feature dimension includes a second trench width at least 2 times greater than the first trench width.