US 12,463,076 B2
3D semiconductor device and structure
Zvi Or-Bach, Haifa (IL); Brian Cronquist, Klamath Falls, OR (US); and Deepak C. Sekar, Sunnyvale, CA (US)
Assigned to Monolithic 3D Inc., Allen, TX (US)
Filed by Monolithic 3D Inc., Klamath Falls, OR (US)
Filed on Mar. 8, 2021, as Appl. No. 17/195,628.
Application 17/195,628 is a continuation in part of application No. 16/537,564, filed on Aug. 10, 2019.
Application 16/537,564 is a continuation in part of application No. 15/460,230, filed on Mar. 16, 2017, granted, now 10,497,713, issued on Dec. 3, 2019.
Application 15/460,230 is a continuation in part of application No. 14/821,683, filed on Aug. 7, 2015, granted, now 9,613,844, issued on Apr. 4, 2017.
Application 14/821,683 is a continuation in part of application No. 13/492,395, filed on Jun. 8, 2012, granted, now 9,136,153, issued on Sep. 15, 2015.
Application 13/492,395 is a continuation of application No. 13/273,712, filed on Oct. 14, 2011, granted, now 8,273,610, issued on Sep. 25, 2012.
Application 13/273,712 is a continuation in part of application No. 12/970,602, filed on Dec. 16, 2010, granted, now 9,711,407, issued on Jul. 18, 2017.
Prior Publication US 2021/0193498 A1, Jun. 24, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/683 (2006.01); G11C 8/16 (2006.01); H01L 21/74 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/525 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01); H10B 20/00 (2023.01); H10B 20/25 (2023.01); H10B 41/20 (2023.01); H10B 41/40 (2023.01); H10B 41/41 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01); H10D 10/01 (2025.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 84/90 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01); H10D 88/00 (2025.01); H10D 89/10 (2025.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)
CPC H01L 21/6835 (2013.01) [G11C 8/16 (2013.01); H01L 21/743 (2013.01); H01L 21/76254 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5252 (2013.01); H10B 10/00 (2023.02); H10B 10/125 (2023.02); H10B 12/053 (2023.02); H10B 12/09 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 20/00 (2023.02); H10B 20/25 (2023.02); H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 41/41 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02); H10D 10/051 (2025.01); H10D 30/0411 (2025.01); H10D 30/0413 (2025.01); H10D 30/0512 (2025.01); H10D 30/60 (2025.01); H10D 30/681 (2025.01); H10D 30/69 (2025.01); H10D 30/711 (2025.01); H10D 30/792 (2025.01); H10D 64/027 (2025.01); H10D 64/513 (2025.01); H10D 84/0172 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 84/907 (2025.01); H10D 84/998 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01); H10D 88/00 (2025.01); H10D 88/01 (2025.01); H10D 89/10 (2025.01); H01L 23/3677 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2221/68368 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/83894 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/01002 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01018 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/01066 (2013.01); H01L 2924/01068 (2013.01); H01L 2924/01077 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/12033 (2013.01); H01L 2924/12036 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1301 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1579 (2013.01); H01L 2924/16152 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/30105 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3025 (2013.01); H10B 12/05 (2023.02); H10D 86/0214 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01)] 17 Claims
OG exemplary drawing
 
1. A 3D semiconductor device, the device comprising:
a first wafer comprising a first level, said first level comprising a first single crystal layer and first transistors,
wherein said first transistors each comprise a single crystal channel;
first metal layers interconnecting at least said first transistors; and
a second wafer comprising a second level, said second level comprising a second single crystal layer and second transistors,
wherein said second level overlays said first level,
wherein said second wafer is hybrid bonded to said first wafer,
wherein said bonded comprises oxide to oxide bonds,
wherein said bonded additionally comprises simultaneous metal to metal bonds made on a same level as the oxide to oxide bonds,
wherein at least one of said first transistors is capable of operating with a first voltage as a maximum operating first voltage,
wherein at least one of said second transistors is capable of operating with a second voltage as a maximum operating second voltage, and
wherein said first voltage is much greater than said second voltage.
 
8. A 3D semiconductor device, the device comprising:
a first wafer comprising a first level, said first level comprising a first single crystal layer and first transistors,
wherein said first transistors each comprise a single crystal channel;
first metal layers interconnecting at least said first transistors; and
a second wafer comprising a second level, said second level comprising a second single crystal layer and second transistors,
wherein said second level overlays said first level,
wherein said second wafer is hybrid bonded to said first wafer,
wherein said bonded comprises oxide to oxide bonds,
wherein said bonded additionally comprises simultaneous metal to metal bonds made on a same level as the oxide to oxide bonds,
wherein at least one of said second transistors comprises hafnium oxide,
wherein at least one of said first transistors is capable of operating with a first voltage as a maximum operating first voltage,
wherein at least one of said second transistors is capable of operating with a second voltage as a maximum operating second voltage, and
wherein said first voltage is much greater than said second voltage.
 
9. A 3D semiconductor device, the device comprising:
a first wafer comprising a first level, said first level comprising a first single crystal layer and first transistors,
wherein said first transistors each comprise a single crystal channel;
first metal layers interconnecting at least said first transistors; and
a second wafer comprising a second level, said second level comprising a second single crystal layer and second transistors,
wherein said second level overlays said first level,
wherein said second wafer is hybrid bonded to said first wafer,
wherein said bonded comprises oxide to oxide bonds,
wherein said bonded additionally comprises simultaneous metal to metal bonds made on a same level as the oxide to oxide bonds,
wherein at least one of said second transistors comprises hafnium oxide,
wherein each of said second transistors are horizontally oriented, and
wherein each of said second transistors comprise at least two side gates.
 
10. A 3D semiconductor device, the device comprising:
a first wafer comprising a first level, said first level comprising a first single crystal layer and first transistors,
wherein said first transistors each comprise a single crystal channel;
first metal layers interconnecting at least said first transistors; and
a second wafer comprising a second level, said second level comprising a second single crystal layer and second transistors,
wherein said second level overlays said first level,
wherein said second wafer is hybrid bonded to said first wafer,
wherein said bonded comprises oxide to oxide bonds,
wherein said bonded additionally comprises simultaneous metal to metal bonds made on a same level as the oxide to oxide bonds,
wherein at least one of said second transistors comprises hafnium oxide,
wherein said device comprises an array of memory cells,
wherein a plurality of said memory cells comprise at least two of said second transistors, and
wherein said first level comprises a periphery circuit to control said array of memory cells.
 
11. A 3D semiconductor device, the device comprising:
a first wafer comprising a first level, said first level comprising a first single crystal layer and first transistors,
wherein said first transistors each comprise a single crystal channel;
first metal layers interconnecting at least said first transistors; and
a second wafer comprising a second level, said second level comprising a second single crystal layer and second transistors,
wherein said second level overlays said first level,
wherein said second wafer is hybrid bonded to said first wafer,
wherein said bonded comprises oxide to oxide bonds,
wherein said bonded additionally comprises simultaneous metal to metal bonds made on a same level as the oxide to oxide bonds,
wherein at least one of said second transistors comprises hafnium oxide,
wherein at least one of said second transistors is an N-type transistor, and
wherein at least one of said second transistors is a P-type transistor.