US 12,463,069 B2
Wafer temperature control device, wafer temperature control method, and wafer temperature control program
Daisuke Hayashi, Kyoto (JP); and Kotaro Takijiri, Kyoto (JP)
Assigned to HORIBA STEC, Co., Ltd., Kyoto (JP)
Filed by HORIBA STEC, Co., Ltd., Kyoto (JP)
Filed on Oct. 11, 2023, as Appl. No. 18/484,626.
Claims priority of application No. 2022-169033 (JP), filed on Oct. 21, 2022.
Prior Publication US 2024/0136212 A1, Apr. 25, 2024
Prior Publication US 2024/0234186 A9, Jul. 11, 2024
Int. Cl. H01L 21/67 (2006.01); G05D 23/19 (2006.01)
CPC H01L 21/67248 (2013.01) [G05D 23/1919 (2013.01); H01L 21/67103 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A wafer temperature control device in which a wafer is placed on a plate having a temperature regulated, and that controls a temperature of the wafer by supplying a heat transfer gas between the plate and the wafer, the wafer temperature control device comprising:
a pressure regulator configured to regulate a pressure of the heat transfer gas;
a nearby temperature sensor configured to measure a temperature near the wafer;
a temperature estimation observer configured to estimate the temperature of the wafer based on a nearby temperature measured by the nearby temperature sensor, and a manipulated pressure variable input to the pressure regulator or a pressure regulated by the pressure regulator; and
a controller configured to control the manipulated pressure variable based on a temperature setting for the wafer and an estimated wafer temperature estimated by the temperature estimation observer, wherein
the temperature estimation observer is configured to use a state-space model in which the temperature of the wafer and the pressure of the heat transfer gas has a linear relationship, and
the controller is configured to correct the temperature setting using a non-linear relationship between the temperature of the wafer and the pressure of the heat transfer gas, the non-linear relationship being acquired in advance, and to control the manipulated pressure variable so as to reduce a temperature deviation between a corrected temperature setting and the estimated wafer temperature.