| CPC H01L 21/3088 (2013.01) [H01L 21/3085 (2013.01); H01L 21/3086 (2013.01); H10D 62/292 (2025.01); H10D 84/0128 (2025.01); H10D 84/0151 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01)] | 21 Claims |

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7. A semiconductor structure forming method, comprising:
providing a base, comprising a target layer, wherein the base comprises target areas for forming target pattern layers and cutting areas corresponding to cutting positions;
forming discrete mask spacers on the base;
patterning the target layer using the mask spacers as masks, to form discrete initial pattern layers, wherein the initial pattern layers extend along a lateral direction, a direction perpendicular to the lateral direction is a longitudinal direction, and grooves are formed between the longitudinally adjacent initial pattern layers;
forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and the cutting areas along the lateral direction;
forming spacing layers filled into the grooves and the boundary defining grooves; and
using the spacing layers located in the boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral direction and the longitudinal direction respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.
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