US 12,463,047 B2
Methods for forming stacked layers and devices formed thereof
Shih-Yao Lin, New Taipei (TW); Kuei-Yu Kao, Hsinchu (TW); Chen-Ping Chen, Toucheng Township (TW); and Chih-Han Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 26, 2024, as Appl. No. 18/587,477.
Application 18/587,477 is a continuation of application No. 17/818,608, filed on Aug. 9, 2022, granted, now 11,942,363.
Application 17/818,608 is a continuation of application No. 16/870,389, filed on May 8, 2020, granted, now 11,488,858, issued on Nov. 1, 2022.
Claims priority of provisional application 62/927,547, filed on Oct. 29, 2019.
Prior Publication US 2024/0243011 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 21/768 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H01L 21/02 (2006.01)
CPC H01L 21/30655 (2013.01) [H01L 21/30608 (2013.01); H01L 21/76831 (2013.01); H10D 84/0128 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H01L 21/02236 (2013.01); H01L 21/02247 (2013.01); H01L 21/02381 (2013.01); H01L 21/0243 (2013.01); H01L 21/0245 (2013.01); H01L 21/02488 (2013.01); H01L 21/02507 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first semiconductor layer;
forming a passivation layer over the first semiconductor layer;
forming a second semiconductor layer over the passivation layer;
removing the first semiconductor layer and the passivation layer to leave a space under the second semiconductor layer; and
forming a gate stack, with a portion of the gate stack being in the space.