US 12,463,043 B2
Wafer processing method
Chun-Fu Wu, Hsinchu (TW); Shih-Ping Lee, Hsinchu (TW); Yu-Chun Huo, Hsinchu County (TW); Chih Feng Sung, Hsinchu (TW); and Ming-Jui Tsai, Hsinchu (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on May 23, 2023, as Appl. No. 18/322,579.
Claims priority of application No. 112114576 (TW), filed on Apr. 19, 2023.
Prior Publication US 2024/0355628 A1, Oct. 24, 2024
Int. Cl. H01L 21/304 (2006.01); H01L 21/683 (2006.01); H01L 21/306 (2006.01); H01L 21/50 (2006.01)
CPC H01L 21/304 (2013.01) [H01L 21/6836 (2013.01); H01L 21/30625 (2013.01); H01L 21/50 (2013.01); H01L 21/683 (2013.01); H01L 21/6835 (2013.01); H01L 2221/6834 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A wafer processing method, comprising:
forming a release layer on a first wafer;
forming an adhesive layer on a second wafer, wherein one of the first wafer and the second wafer is a device wafer, and the device wafer comprises a valid die region and a trimming region;
placing the first wafer on the second wafer by a handler, so that the release layer and the adhesive layer are bonded to each other, and the adhesive layer completely covers the valid die region, wherein during the process of placing the first wafer on the second wafer, the handler directly moves the first wafer;
bonding one of the first wafer and the second wafer that is the device wafer to a third wafer; and
removing the release layer to separate the first wafer from the second wafer, wherein the release layer is removed by a laser.