US 12,463,039 B2
Method for reducing parasitic junction field effect transistor resistance
Bing-Yue Tsui, Hsinchu (TW); and Jui-Cheng Wang, Hsinchu (TW)
Assigned to NATIONAL YANG MING CHIAO TUNG UNIVERSITY, Hsinchu (TW)
Filed by National Yang Ming Chiao Tung University, Hsinchu (TW)
Filed on Aug. 1, 2022, as Appl. No. 17/878,575.
Claims priority of application No. 111117126 (TW), filed on May 6, 2022.
Prior Publication US 2023/0360916 A1, Nov. 9, 2023
Int. Cl. H01L 21/266 (2006.01); H10D 12/00 (2025.01); H10D 30/66 (2025.01)
CPC H01L 21/266 (2013.01) [H10D 12/441 (2025.01); H10D 30/66 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A method for reducing parasitic junction field effect transistor resistance, which is applicable to a high power device including a semiconductor substrate layer, the method comprising:
providing a plurality of hard masks on a top surface of the semiconductor substrate layer, wherein each of the plurality of hard masks includes a bottom plane and a tilt sidewall, and an acute angle is formed between the tilt sidewall and the bottom plane; and
performing a body ion implantation process, such that at least one body region is formed between adjacent two of the plurality of hard masks in the semiconductor substrate layer, the at least one body region has an upper surface and a lower surface, and a width of the upper surface is greater than that of the lower surface, wherein between the upper surface and the lower surface of the body region is a connecting sidewall, both the connecting sidewall of the body region and the tilt sidewall of the hard mask have a sloped sidewall, and a slope of the connecting sidewall of the body region is the same as the slope of the tilt sidewall of the hard mask.