| CPC H01L 21/26506 (2013.01) [H01L 21/30625 (2013.01); H01L 21/76898 (2013.01)] | 16 Claims |

|
1. A method of fabricating a semiconductor device having active devices connected with a backside power delivery system, comprising:
implanting a marking species into a front side of a workpiece to create a Chemical Mechanical Planarization (CMP) marker layer, wherein the CMP marker layer has a peak concentration of the marking species at a first depth;
implanting a first species of ions into the front side of the workpiece such that a peak concentration of the first species of ions is at a second depth, greater than the first depth, wherein the first species of ions suppress diffusion of the marking species, wherein the first depth and the second depth are referenced to a same surface of the workpiece such that the first species of ions travel deeper into the workpiece than the marking species;
performing front end of line (FEOL) processes on the front side of the workpiece to create the active devices;
performing back end of line (BEOL) processes to create metallization layers on the front side of the semiconductor device;
thinning the workpiece using a CMP process on a backside of the workpiece, wherein the CMP process slows when the CMP marker layer is exposed;
creating nano through silicon vias (nTSVs) to expose the active devices within the semiconductor device; and
adding metallization layers to the back side of the workpiece, wherein the metallization layers contact the active devices.
|