US 12,462,893 B2
Conductance modulation in computational memory
Ghazi Sarwat Syed, Kilchberg (CH); Benedikt Kersting, Lüdinghausen (DE); and Abu Sebastian, Adliswil (CH)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 14, 2023, as Appl. No. 18/368,158.
Prior Publication US 2025/0095764 A1, Mar. 20, 2025
Int. Cl. G11C 29/52 (2006.01); G11C 11/56 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 11/5678 (2013.01); G11C 2207/2254 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
determining a plurality of conductance values for a plurality of unit cells arranged in a crossbar arrangement, wherein the plurality of unit cells comprises non-volatile memory (NVM) devices, and the plurality of conductance values are less than maximum conductance values of the plurality of unit cells;
using the plurality of conductance values to perform a programming operation to map a plurality of calibration weights to the plurality unit cells;
using an initial value of a read gate voltage to perform a read operation to read the plurality of calibration weights from the plurality of unit cells;
determining an error of a compute result of the read operation;
based on the determined error, adjusting the initial value of the read gate voltage to determine a read gate voltage for driving a plurality of access transistors to read from the plurality of unit cells; and
mapping a plurality of weights to the determined plurality of conductance values and to the determined read gate voltage.